Multi-Patterning

Computer chips are made by printing tiny patterns onto round silicon wafers. This happens with light, similar to a photographic print: light falls through a stencil onto a light-sensitive layer and traces lines there. How fine these lines can become depends on the wavelength of the light — at some point, two lines that lie too close together blur into one. Multi-patterning gets around this limit. Instead of printing all the lines at once, they are spread across two, three, or four passes, each of which leaves enough spacing. Layered on top of each other, the passes ultimately produce a pattern finer than any single pass could achieve.

Why the chip industry would have stalled without this workaround

For decades, chips became faster and more efficient because their structures kept shrinking. This miniaturization worked as long as finer light was available for each new generation. Around 2012, that stalled: the industry was exposing with light at a wavelength of 193 nanometers and had no replacement for it for a long time. But the desired structures were already significantly smaller.

Multi-patterning solved this problem without requiring new machines. Using the same exposure equipment, it suddenly became possible to manufacture chips at 14, 10, and even 7 nanometers. Without this workaround, the shrinking of chips would have paused for years — with consequences for smartphones, data centers, and AI hardware.

The price for this is high. Every additional pass means more machine time, more expensive stencils, and more opportunities for errors. Chips with many multi-patterning steps are therefore more expensive per unit, and the yield of functioning chips drops. Economically, this has long been the main brake on shrinking structures.

Two paths to finer lines

The simplest variant is called double patterning via double exposure. The desired pattern is conceptually split into two halves. Each half contains only every other line and is therefore loose enough for the machine. First one half is exposed and etched, then the other. Experts call this sequence LELE, short for Litho-Etch-Litho-Etch.

The second variant works without a second exposure and is called the spacer process. First, comparatively coarse bars are printed. A thin layer is deposited onto their sidewalls, and then the bars are removed. What remains are the sidewalls as narrow ridges — twice as many as there were original bars. The width of these ridges depends only on the thickness of the layer, no longer on the light.

The decisive catch is overlay alignment. The individual passes must line up with each other to within a few nanometers. If the second exposure shifts slightly, the spacing becomes uneven and the circuit no longer works reliably. Chip design must also be adapted: software breaks the layout down into sub-patterns beforehand, and not every shape can be cleanly split apart.

Multi-patterning in chip manufacturing news

The term comes up when discussing manufacturing processes at TSMC, Samsung, or Intel. Reports like “The new process requires fewer multi-patterning steps” are essentially statements about cost. Fewer passes mean faster production and more usable chips per wafer.

Closely related to this topic is EUV, exposure using extreme ultraviolet light with a wavelength of 13.5 nanometers. EUV makes many multi-patterning steps unnecessary because it can print fine structures directly. Worldwide, only the Dutch company ASML builds the machines for this, and each one costs several hundred million euros. This is precisely why export bans on EUV equipment remain a persistent political issue.

A common misconception is that EUV has replaced multi-patterning. For the most advanced processes below 3 nanometers, even EUV alone is no longer sufficient, and the two are combined. Chipmakers without access to EUV equipment, in turn, push multi-patterning to its limits in order to achieve similarly small structure sizes — more expensive and with lower yield, but technically possible.