Backside Power Delivery
Backside Power Delivery is a method in which a computer chip's power lines are relocated to the back side of the silicon die. This creates more room for data lines on the front side while simultaneously making chips faster and more energy-efficient.
A modern chip consists of billions of tiny switches, the transistors, which are interconnected through a dense network of ultra-thin metal wires. Power that drives the transistors in the first place also flows through this same network. For a long time, data lines and power lines sat on the same side of the chip — competing for the same scarce space. Backside Power Delivery solves this problem by moving the power lines to the back side of the silicon die. The front and back sides thus take on clearly separated tasks.
Why space on the chip is so valuable
The chip industry has followed a simple principle for decades: more transistors on the same area means more performance. But the more densely the transistors are packed, the tighter it also gets for the wires around them. Until now, engineers had to weigh, for every new chip, how much space to reserve for data lines versus power lines — a trade-off that kept getting harder.
On top of that comes a physical problem: if a power line is too long or too thin, resistance arises. Resistance generates heat and costs energy. The shorter the path from the power grid to the transistor, the fewer the losses. Backside Power Delivery significantly shortens this path, because power can be fed directly into the transistor from below, without first having to thread its way across the data-line layers.
How the back side of the chip is being opened up
In the classic setup, a chip grows from the bottom up: first the transistors form in the silicon, then layer by layer the metal levels with the wiring are added on top. In Backside Power Delivery, after manufacturing the silicon die is ground down from below until the underside of the transistors is exposed. New metal layers are then applied there — exclusively for power.
That sounds simple, but is extremely demanding to actually pull off. The silicon must not crack in the process, and the new lines must connect at exactly the right spots, accurate to the nanometer. Intel calls its process “PowerVia” and first demonstrated it in a test chip in 2023. TSMC and Samsung are working on their own variants, which are expected to go into mass production in the second half of the 2020s.
The gain is measurable: in initial tests, Intel reported roughly six percent higher clock frequency and markedly more uniform power delivery across the entire chip area. The latter matters because voltage fluctuations can cause computational errors and previously had to be compensated for with safety margins — margins that can now be made smaller.
Where Backside Power Delivery shows up
In tech news, the term comes up mainly in connection with the next generation of high-performance chips. Intel’s processors built on its “18A” process, planned from 2025 onward, are expected to be the first mass-market products with Backside Power Delivery. Apple, Qualcomm, and Nvidia are being mentioned as possible customers for corresponding TSMC processes.
For everyday users, the technology will become noticeable indirectly: laptops with such chips could become faster at the same battery life — or last longer at the same speed. In data centers, where power is one of the biggest cost factors, the efficiency gains are likely to matter especially.
Backside Power Delivery is not a single product you can buy, but a manufacturing process that sits invisibly inside future chips. It is a prime example of how the chip industry keeps developing ever more sophisticated tricks to push back the physical limits of miniaturization — even if only by another small step.